Semiconductor memory devices are used in a wide variety of applications. Such memory devices receive data for storage, in what is called a Write operation, and provide stored data to devices external to the memory, in what is called a Read operations. Typically, the memory device is accessed through a bus or multiple bus system by an external device or bus-master, such as a microprocessor, memory controller, or application specific integrated circuit (ASIC). The bus transfers address, data, and control signals between the memory device and the bus-master accessing the memory device.
The operation of many of today's high speed memory devices, such as synchronous dynamic random access memories ("SDAMs"), synchronous link DRAMs ("SLDRAMs") and RAMBUS DRAMs ("RDRAMS"), is controlled by one or more clock signals. The clock signal synchronizes the operation of the memory device to other device, such as memory controllers, and it synchronizes the operation of circuits within the memory device to each other.
Although the operating speeds of some portions of a memory device are controlled by the frequency of the clock signal, some operations in a memory device inherently require a fixed period of time. For example, the minimum period of time required for write data to be coupled to the array of a memory device or for read data to the coupled from the array of a memory device is substantially fixed. Thus, the number of clock periods occurring during the time required for data to be coupled to or from the array is directly proportional to the clock frequency. For this reason, there may be no fixed relationship between the timing of control signals that cause the data to be coupled to or from the array at the maximum rate and the number of clock signals occurring during that time.
The control signals could be generated simply by generating the control signals after a fixed number of clock periods have elapsed corresponding to the period required for the memory operation at the highest clock frequency that will be used with the memory device. However, this approach would cause the memory device to operate at less than optimal speed when a lower frequency clock signal was used. For example, a memory operation requiring 100 ns to complete might require a control signal to be generated after 10 clock periods using a clock signal having a period of 10 ns. However, when the memory device was used with a clock signal having a clock period of 50 ns, the same control signal would be generated after 500 ns, which is 400 ns slower than the memory device would be capable of operating. As a result, it can be difficult to generate control signals to cause memory operations to occur at the maximum rate when the memory device operates at a variable clock speed.